The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a middle-of-the-line (MOL) air gap contact positioned over a source/drain region that comes into contact (i.e., touches) a portion of a functional gate structure, and a method of forming such a semiconductor structure.
Field effect transistors (FETs) are the basic building block of today's integrated circuits. Such transistors can be formed in conventional bulk substrates (such as silicon) or in semiconductor-on-insulator (SOI) substrates. State of the art FETs can be fabricated utilizing a gate-first process or a gate-last process. In a gate-first process, a gate material stack is first formed, followed by the formation of source/drain regions. In a gate-last process, the source/drain regions are formed prior to replacing a sacrificial gate structure with a functional gate structure.
In either process, a gate spacer composed of a dielectric material such as, for example, silicon dioxide, is typically present on the vertical sidewalls of the functional gate structure. The presence of a gate spacer is a source of parasitic capacitance that is under the Miller effect. There have been proposal to replace conventional gate spacers with air gap spacers. However, all proposals known to date involve utilizing a sacrificial gate spacer which is formed prior to formation of the source/drain regions and then removed sometime after source/drain formation. Such a process is very difficult and is not very manufacturable.
In view of the above, there is a continued need for providing FETs in which a gate dielectric spacer is not present and which includes a method that is easy to implement and is manufacturably feasible.